CSCI-B 543 Computer Architecture
3 credits
- Prerequisite(s): CSCI-C 335 and 343 or honors versions; ECE 36500 or CS 40200
- Delivery: On-Campus
- Semesters offered: Spring (Check the schedule to confirm.)
- Equivalent(s): CSCI 50400 Concepts in Computer Organization and ECE 56500 Computer Architecture
Description
Fundamentals of computer design, instruction processing, and performance analysis. Single-processor systems’ architecture focuses on pipelining, memory and memory hierarchies, and interconnect technology. Exploration of architecture classes such as high-performance multiprocessors, massively parallel computers, and embedded systems.
Topics
Introduction to computer architecture
- Fundamental concepts and principles
- Quantitative aspects of computer design and analysis
- Computers classified by application, performance, and architectural features
Design computing platforms
- Role of computer architecture in system design
Memory hierarchy and design principles
- Essential components
- Memory hierarchy and its function
- Trade-offs for optimal performance
Advanced memory optimizations
- Methods to enhance cache memory performance
- Reducing cache miss rates and optimizing cache utilization
- Memory technologies: DRAM and SRAM
Virtual memory systems
- Memory-related optimizations
- Virtual memory and virtual machines
Instruction-level parallelism (ILP)
- Challenges in extracting parallelism from sequential code
- Techniques and factors affecting ILP exploitation
ILP compiler techniques and hardware approaches
- Compiler techniques for code reorganization to achieve parallelism
- Hardware approaches for dynamic parallel instruction execution
Case studies
- Intel Core i7
- ARM Cortex-A8
Data-level parallelism (DLP)
- Computational efficiency
- Architectures: vector architectures, SIMD instruction sets, GPUs
Optimizing data-level parallelism
- Enhancing DLP in computer programs
- Identifying and optimizing loop-level parallelism
Multiprocessor architectures
- Centralized shared-memory multiprocessor architectures
- Distributed shared-memory architectures
- Directory-based coherence protocols for cache consistency
Inter-processor communication and synchronization
- Communication in distributed memory systems
- Synchronization for resource access
- Memory consistency models
Warehouse-scale computers (WSC)
- Request-level and data-level parallelism
- Programming models and workloads
Large-scale workloads and cloud computing
- Principles of computer architecture for large-scale workloads
- Design and hardware configurations
Energy efficiency and fault tolerance
- Scalability considerations
Learning Outcomes
- Analyze single and multiprocessor systems' hardware organization and architectural features to determine their strengths and weaknesses in meeting specific design goals. CS 3
- Evaluate and compare the performance of instruction-level and fine-thread level parallelisms in processors and propose optimizations to enhance parallel execution efficiency in complex computing tasks. CS 3
- Evaluate the effectiveness of different branch prediction mechanisms, considering their impact on processor performance and exploring innovative approaches for improving branch prediction accuracy. CS 3
- Analyze the execution pipeline of instructions in a processor, identifying potential hazards and proposing advanced pipelining techniques to mitigate bottlenecks and enhance overall performance. CS 3
- Analyze and critique the various components within the memory hierarchy, such as cache systems and virtual memory, to optimize memory access times, reduce latency, and design efficient memory architectures that align with specific application requirements. CS 3
- Design novel approaches for enhancing single and multiprocessor systems' performance and efficiency, considering power consumption, scalability, and cost-effectiveness trade-offs to meet specific design objectives. CS 3
- Communicate performance gain strategies for GPU acceleration and optimization techniques in real-world applications, providing an analysis of their results. CS 6
Policies and Procedures
Please be aware of the following linked policies and procedures. Note that in individual courses instructors will have stipulations specific to their course.